An electronic circuit (e.g., a Very-Large-Scale-Integration (VLSI) circuit) may include several elements and interconnectors thereof. The elements (e.g., memories) may be prone to manufacturing defects due to dense packing therein and/or complex design thereof. A Built-In Self-Test (BIST) may be implemented during the verification of a design of the electronic circuit to test for the aforementioned manufacturing defects. The BIST may involve executing several algorithms on the elements to detect different types of structural faults. The aforementioned simulation may have a large runtime associated therewith as an entire address space of each element is covered for all the algorithms.